In recent years, high-speed differential interface circuits are used in various types of devices. For instance, in the field of TFT_LCD (Thin Film Transistor Liquid Crystal Display), as interfaces between LCD driver LSI and timing controller LSI, RSDS (Reduced Swing Differential Signaling: a registered trademark of National Semiconductor Corporation) and mini-LVDS (mini Low Voltage Differential Signaling: a registered trademark of Texas Instruments, Inc.) are becoming standardized. The voltage comparator circuits with differential inputs are used in the receiver circuits of these technologies.
The frequencies of the differential signal inputted into the voltage comparator circuits are approximately 85 MHz and 200 MHz in the cases of RSDS and mini-LVDS respectively. The input differential voltages of the differential signal component and in-phase signal component are ±50 mV and approximately 0.3V to VDD-0.5V respectively.
A circuit that meets these specifications, as the characteristics required for a voltage comparator circuit, is demanded. However, with the circuit configuration currently available, it is difficult to meet the standards of the in-phase signal component and have a satisfying operation speed simultaneously.
FIG. 6 shows the configuration of a differential amplifier circuit described in Non-Patent Document 1 (IEEE J. Solid-State Circuits. vol. 29 No. 12. December 1994, pp. 1505 to 1513 “A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries”).
In reference to FIG. 6, this differential amplifier comprises a differential amplifier circuit, comprising a first differential pair of a first P-channel MOS transistor MP1 and a second P-channel MOS transistor MP2 and a second differential pair of a first N-channel MOS transistor MN1 and a second N-channel MOS transistor MN2, a third and fourth N-channel MOS transistors MN3 and MN4, connected to a first voltage source V1, wherein their respective gates are connected in common, a third and fourth P-channel MOS transistors MP3 and MP4 wherein their respective gates and sources are connected in common, a fifth and sixth P-channel MOS transistors MP5 and MP6, connected to a second voltage source V2, wherein their respective gates are connected in common, a first constant current source (supplying a current I1) connected between a source connected in common to the first differential pair (MP1 and MP2) and a positive power source VDD, a second constant current source (supplying a current I2) connected between a source connected in common to the second differential pair (MN1 and MN2) and a negative power source, a third constant current source (supplying a current I3) connected between the source of the third N-channel MOS transistor MN3 and the negative power source, and a fourth constant current source (supplying a current I4) connected between the source of the fourth N-channel MOS transistor MN4 and the negative power source.
The drains of the first and second P-channel MOS transistors MP1 and MP2, which constitute the first differential pair, are connected to the sources of the third and fourth N-channel MOS transistors MN3 and MN4 respectively.
The drain of the first N-channel MOS transistor MN1, which constitutes the second differential pair, the drain of the third P-channel MOS transistor MP3, and the source of the fifth P-channel MOS transistor MP5 are connected in common, and the drain of the second N-channel MOS transistor MN2, which constitutes the second differential pair, the drain of the fourth P-channel MOS transistor MP4, and the source of the sixth P-channel MOS transistor MP6 are connected in common.
The gate of the third P-channel MOS transistor MP3, the drain of the fifth P-channel MOS transistor MP5, and the drain of the third N-channel MOS transistor MN3 are connected in common.
The gate of the first N-channel MOS transistor MN1 and the gate of the first P-channel MOS transistor MP1 are connected in common to a noninverting input terminal, and the gate of the second N-channel MOS transistor MN2 and the gate of the second P-channel MOS transistor MP2 are connected in common to an inverting input terminal.
The drain of the sixth P-channel MOS transistor MP6 and the drain of the fourth N-channel MOS transistor MN4 are connected in common to an output terminal.
Voltage comparator circuit is an application of differential amplifier, and the conventional differential amplifier shown in FIG. 6 can be used as a voltage comparator circuit. However, when the differential amplifier shown in FIG. 6 is practically used as a voltage comparator circuit, waveform shaping is necessary.
For the purpose of waveform shaping, CMOS inverters must be connected after this differential amplifier circuit.
FIG. 9 shows a concrete configuration of the above idea. In reference to FIG. 9, the input terminal of a first CMOS inverter INV1 is connected to the output of the differential amplifier. After the first CMOS inverter INV1, second and third CMOS inverters INV2 and INV3 are connected in series for the purpose of further waveform shaping, and the output of the third CMOS inverter INV3 becomes the final output.
FIG. 10 is a drawing showing a concrete example of the circuit configuration of the CMOS inverter shown in FIG. 9. In reference to FIG. 10, the CMOS inverter comprises a P-channel MOS transistor MP1 whose source is connected to a positive power source VDD, an N-channel MOS transistor MN1 whose drain is connected to the drain of the P-channel MOS transistor MP1 and to an output terminal, and source is connected to a negative power source VSS (GND), and the gates of the P-channel MOS transistor MP1 and the N-channel MOS transistor MN1 are connected in common and connected to an input terminal.
Hereinafter, the use of this differential amplifier as a voltage comparator circuit will be analyzed. First, the basic operation of a differential amplifier comprised of MOS transistors is explained with reference to FIGS. 7 and 8. FIG. 7 shows a basic circuit configuration of a differential amplifier circuit, and FIG. 8 shows the direct current transmission characteristics of its input voltage/output current. The sources of N-channel MOS transistors MN1 and MN2 are connected in common, and a constant current source Iss is connected between these sources connected in common and a negative power source. Further, a voltage source Vi1 is connected to the gate of the MN1, and a voltage source Vi2 is connected to the gate of the MN2. The following Equation (1) holds because of the relationship of the input voltage, where the gate-source voltages of the MN1 and MN2 are VGS1 and VGS2 respectively.Vi1−VGS1+VGS2−Vi2=0  (1)
Furthermore, where the drain currents are Id1 and ld2 respectively, the gate width and length are W and L respectively, the mobility is μ, the gate oxide film capacity per unit area is Co, and the threshold value is Vt, the transconductance β (refer to the following Equation (2)), VGS1 and VGS2 (the gate-source voltages of the MOS transistors MN1 and MN2) are given by the following Equations (3) and (4).
                    β        =                              W            L                    ⁢          μ          ⁢                                          ⁢                      C            0                                              (        2        )                                          V          GS1                =                                                            2                ⁢                                  I                  d1                                            β                                +                      V            T                                              (        3        )                                          V          GS2                =                                                            2                ⁢                                  I                  d2                                            β                                +                      V            T                                              (        4        )            
Here, a differential voltage ΔVid with which the bias current Iss is completely switched to the transistor MN1 is calculated from Equations (1), (3), and (4) as in the following Equation (5).
                              Δ          ⁢                                          ⁢                      V            id                          =                                            V              i1                        -                          V              i2                                =                                                    (                                                                                                    2                        ⁢                                                  I                          SS                                                                    β                                                        +                                      V                    T                                                  )                            -                              V                T                                      =                                                            2                  ⁢                                      I                    SS                                                  β                                                                        (        5        )            
Further, where VGS0 is the gate-source voltage VGS when Vi1=Vi2, the drain currents of the MN1 and MN2 become Iss/2 respectively and the following Equation (6) is obtained.
                              V          GS01                =                                                            I                SS                            β                                +                      V            T                                              (        6        )            
Therefore, the following Equation (7) is given from Equations (5) and (6).ΔVid=√{square root over (2)}(VGS0−VT)  (7)
This Equation (7) is a conditional equation for when the MOS differential stage is completely switched. As described above, when the input differential voltage is higher than the value represented by Equation (7), the bias current source of the differential stage flows in one of the transistors and the current of the other transistor becomes zero. This provides a comparator operation.
However, even if it is not switched completely as described above, depending on the structure of a stage after this differential stage, a comparator operation can be obtained with a lower differential voltage than this. It is because this differential stage has enough gain. FIG. 8 shows a relation graph between the input voltage and the drain current, which constitutes the differential stage.
A detailed explanation on the differential amplifier shown in FIG. 6 will be given. The differential amplifier shown in FIG. 6 is a so-called folded cascode-type differential amplifier circuit.
This circuit has the following three operation modes, depending on the input voltage range.
[1]<When Both the First and Second Differential Pairs are Operating>
Where Vin is the input voltageVDD−(VGS(MP1/2)+VDS(sat)(I1))>Vin>VGS(MP1/2)+VDS(sat)(I2)  (8)
and where
VGS(MN1/2): the gate-source voltages of the N-channel MOS transistors MN 1/2,
VDS(sat)(I2): the drain-source voltage of the N-channel MOS transistor, which constitutes the current source I2, at the saturation point (a minimum voltage needed for the operation in the pentode region),
VGS(MP1/2): the gate-source voltages of the P-channel MOS transistors MP 1/2, and
VDS(sat)(I1): the drain-source voltage of the P-channel MOS transistor, which constitutes a current source I1, at the saturation point (a minimum voltage needed for the operation in the pentode region),
and when the above conditions are met, both the first and second differential pairs are in an operating mode.
Assuming a voltage higher than Equation (7) is inputted and it is higher on the side of In+ than that of In−, this circuit operates as a voltage comparator circuit, therefore, all the bias current of the first differential pair (MP1 and MP2) I1 flows to the second P-channel MOS transistor MP2, and the current of the first P-channel MOS transistor MP1 becomes zero. On the other hand, all the bias current of the second differential pair (MN1 and MN2) I2 flows to the first N-channel MOS transistor MN1 and the current of the second N-channel MOS transistor MN2 becomes zero. Looking at the bias current condition of each transistor at this time, the following Equations (9) and (10) hold where ID(MN3) is the drain current of the third N-channel MOS transistor MN3, and ID(MN4) is the drain current of the fourth N-channel MOS transistor MN4:ID(MN4)=I4−I1  (9)ID(MN3)=I3  (10)
Here, the relationship of I1, I3, and I4 is as follows:I3=I4≧I1  (11)
On the other hand, the fifth P-channel MOS transistor MP5's drain current ID(MP5) is the same as the third N-channel MOS transistor MN3's drain current ID(MN3), therefore the following Equation (12) holds:ID(MP5)=ID(MN3)  (12)
Furthermore, the third P-channel MOS transistor MP3's drain current ID(MP3) is obtained by adding the fifth P-channel MOS transistor MP5's drain current ID(MP5) and the first N-channel MOS transistor MN1's drain current ID(MN1)ID(MP5)=I3,ID(MN1)=I2,
therefore, the following Equation (13) holds:ID(MP3)=ID(MP5)+ID(MN1)=I3+I2  (13)
Since the respective gates and sources of the fourth P-channel MOS transistor MP4 and the third P-channel MOS transistor MP3 are connected in common, their drain currents are equal. Therefore, the fourth P-channel MOS transistor MP4's drain current ID(MP4) is given by the following Equation (14):ID(MP4)=ID(MP3)=I3+I2  (14)
Further, the value of the sixth P-channel MOS transistor MP6's drain current ID(MP6) is obtained by subtracting the second N-channel MOS transistor MN2's drain current ID(MN2) from the fourth P-channel MOS transistor MP4's drain current ID(MP4), and since ID(MN2) is zero in this condition, ID(MP6) is given by the following Equation (15):ID(MP6)=ID(MP4)−ID(MN2)=I3+I2  (15)
Since the drain of the sixth P-channel MOS transistor MP6 and the drain of the fourth N-channel MOS transistor MN4 are connected in common to the output terminal, the output current is the subtraction of Equation (9) from Equation (15) described above (ID(MP6)−ID(MN4)). In other words, the output terminal goes to a high level, and the current discharge capability Iout is given by the following Equation (16):Iout=(I3+I2)−(I4−I1)  (16)
Here, I3=I4, and as a result, the output end current Iout has the current discharge capability ofIout=I1+I2  (17)
and it goes to a high level. Potentially it is a VDD, a nearly positive power source.
Next, assuming a voltage higher than Equation (7) is inputted and it is lower on the side of In+ than that of In−, the present circuit operates as a comparator circuit, therefore, all the bias current of the first differential pair I1 flows to the first P-channel MOS transistor MP1, and the current of the second P-channel MOS transistor MP2 becomes zero. On the other hand, all the bias current of the second differential pair I2 flows to the second N-channel MOS transistor MN2 and the current of the first N-channel MOS transistor MN2 becomes zero. The bias current condition of each transistor at this time can be given by the following Equations (18) and (19) where ID(MN3) is the drain current of the third N-channel MOS transistor MN3, and ID(MN4) is the drain current of the fourth N-channel MOS transistor MN4:ID(MN4)=I4  (18)ID(MN3)=I3−I1  (19)
On the other hand, the fifth P-channel MOS transistor MP5's drain current ID(MP5) is the same as the third N-channel MOS transistor MN3's drain current ID(MN3), therefore it is given by the following Equation (20):ID(MP5)=ID(MN3)  (20)
Furthermore, the third P-channel MOS transistor MP3's drain current ID(MP3) is obtained by adding the fifth P-channel MOS transistor MP5's drain current ID(MP5) and the first N-channel MOS transistor MN1's drain current ID(MN1), and in this condition, ID(MP5)=I3, ID(MN1)=0, therefore, the following Equation (21) holds:ID(MP3)=ID(MP5)+ID(MN1)=I3−I1  (21)
Since the respective gates and sources of the fourth P-channel MOS transistor MP4 and the third P-channel MOS transistor MP3 are connected in common, their drain currents are equal. Therefore, the fourth P-channel MOS transistor MP4's drain current ID(MP4) is given by the following Equation (22):ID(MP4)=ID(MP3)=I3−I1  (22)
Further, the value of the sixth P-channel MOS transistor MP6's drain current ID(MP6) is obtained by subtracting the second N-channel MOS transistor MN2's drain current ID(MN2) from the fourth P-channel MOS transistor MP4's drain current ID(MP4), and since ID(MN2)=I2 in this condition, ID(MP6) is given by the following Equation (23):ID(MP6)=ID(MP4)−ID(MN2)=I3−I1−I2  (23)
Similarly, the output current is the subtraction between the current values shown in Equation (18) and Equation (23). In other words, the output end current Iout is given by the following Equation (24) where the current discharged from the output end is positive:Iout=I4−(I3−I1−I2)  (24)
Here, I3=I4, and as a result, the output end current Iout has a current absorption capability ofIout=I1+I2  (25)
and it goes to a low level. Potentially it becomes 0V, nearly a negative power source (GND).
[2]<When Only the First Differential Pair is Operating>
As opposed to the case in [1], when the input voltage Vin in this case is0<Vin<VGS(MN1/2)+VDS(sat)(I2)  (26)only the first differential stage operates. It is because the drain-source voltage of the MOS transistor, which functions as the constant current source that constitutes I2, becomes unavailable, therefore, I2=0. As a result, the second differential stage stops operating. A detailed analysis method is omitted here, but if the drive current at the output terminal (OUT) is analyzed as in the case of [1], both the discharge current and absorption current are given by the following Equation (27):Iout=I1  (27)[3]<When Only the Second Differential Pair is Operating>
As opposed to the case in [1], when the input voltage Vin in this case isVDD>Vin>VDD−(VGS(MP1/2)+VDS(sat)(I1))  (29)only the second differential stage operates. It is because the drain-source voltage of the MOS transistor, which functions as the constant current source that constitutes I1, becomes unavailable, therefore, I1=0. As a result, the first differential stage stops operating. A detailed analysis method is omitted here, but if the drive current at the output terminal (OUT) is analyzed as in the case of [1], both the discharge current and absorption current are given by the following Equation (29):Iout=I2  (29)
As becomes clear from the above, the drive capability of the output directly depends on the bias current values of the differential input stage.
Therefore, the only way to increase drive capability is to increase the bias current of the differential stage. This drive current is used for charging/discharging the parasitic capacitance related to the output of the voltage comparator circuit. Therefore, the operation speed depends on this bias current.
As the input frequency increases, the output of the differential amplifier becomes closer to a sinusoidal wave.
Therefore, a CMOS inverter circuit for converting this output sine wave into a rectangular wave, i.e. wave shaping, is connected after this differential amplifier.
Since the threshold of the CMOS inverter is set to approximately VDD/2, the borderline is when the input waveform of the CMOS inverter crosses VDD/2. When the input waveform of the CMOS inverter is below it, the output goes to a high level (VDD), and when it is above it, the output goes to a low level (VSS (GND)). This is how wave shaping is performed. The reason why there are multiple stages of the CMOS inverters (three stages in this case) is because wave shaping cannot be completed by only one stage.
In Patent Document 1, a structure in which the in-phase input voltage range can be as wide as to be from power supply voltage to GND by synthesizing the outputs of a differential amplifier comprising a P-channel MOS transistor and a differential amplifier comprising a N-channel MOS transistor is disclosed.
[Non-Patent Document 1]
IEEE J. Solid-State Circuits. Vol. 29 No. 12. December 1994, pp. 1505-1513, “A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries.”
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-03-62712
The entire disclosure of these documents is incorporated herein by reference thereto.